Vlsi Design By Kang.epubl
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We present a processing-in-memory (PIM)-based hardware platform, referred to as MONETA, for on-chip acceleration of inference and learning in hybrid convolutional spiking neural network. MONETAuses 8T static random-access memory (SRAM)-based PIM cores for vector matrix multiplication (VMM) augmented with spike-time-dependent-plasticity (STDP) based weight update. The spiking neural network (SNN)-focused data flow is presented to minimize data movement in MONETAwhile ensuring learning accuracy. MONETAsupports on-line and on-chip training on PIM architecture. The STDP-trained convolutional neural network within SNN (ConvSNN) with the proposed data flow, 4-bit input precision, and 8-bit weight precision shows only 1.63% lower accuracy in CIFAR-10 compared to the STDP accuracy implemented by the software. Further, the proposed architecture is used to accelerate a hybrid SNN architecture that couples off-chip supervised (back propagation through time) and on-chip unsupervised (STDP) training. We also evaluate the hybrid network architecture with the proposed data flow. The accuracy of this hybrid network is 10.84% higher than STDP trained accuracy result and 1.4% higher compared to the backpropagated training-based ConvSNN result with the CIFAR-10 dataset. Physical design of MONETAin 65 nm complementary metal-oxide-semiconductor (CMOS) shows 18.69 tera operation per second (TOPS)/W, 7.25 TOPS/W and 10.41 TOPS/W power efficiencies for the inference mode, learning mode, and hybrid learning mode, respectively.
Parhi Research Group SiteResearch is focused on on all aspects of VLSI signal and image processing starting from algorithm and architecture design to design of digital integrated circuits and computer-aided design tools. Our emphasis is on developing techniques to design architectures and algorithms which can be operated with high speed, or lower area or lower power. Different applications impose different speed-power demands on implementations of an identical algorithm. While video and radar applications require high-speed, wireless and personal communications systems applications require low-power implementations. In addition to studying VLSI implementation styles, we also are studying computer arithmetic implementations and design of CAD tools for high-level synthesis of digital signal processing (DSP) systems and for multiprocessor prototyping and task scheduling of software programmable DSP systems using data-flow graph models. Very high-speed architectures are designed based on novel use of look-ahead computations, pipelining and retiming. Recent work has addressed pipelined designs for parallel decision feedback equalizers, Tomlinson-Harashima precoders, Viterbi decoders, linear-feedback shift registers, and multi-gigabit transceivers. Significant research has been directed towards parallel and pipelined implementations of turbo decoders, low-power implementations of low-density parity check codes, and crypto-acclerators. Current research on low-power design is based on implementations using overscaled supply voltage and subthreshold circuit design.
2022 Charles E. Bowers Faculty Teaching Award 2021 IEEE Circuits and Systems Society John Choma Education Award 2020 Association for Computing Machinery (ACM) Fellow for contributions to architectures and design tools for signal processing and networking accelerators2020 Fellow, National Academy of Inventors (NAI)2019-2021 IEEE Circuits and Systems Society Distinguished Lecturer 2017 Fellow, American Association for Advancement of Science (AAAS)2017 Mac Van Valkenburg Award from the IEEE Circuits and Systems Society 2013 Distinguished Alumnus Award, Indian Institute of Technology, Kharagpur2013 Award for Outstanding Contributions to Postbaccalaureate, Graduate, and Professional Education, University of Minnesota2012 Charles A. Desoer Technical Achievement Award from IEEE Circuits and Systems Society 2004 Frederick Emmons Terman Award from the American Society of Engineering Education2003 IEEE Kiyo Tomiyasu Technical Field Award2000 - present Distinguished McKnight University Professorship1997- present Edgar F. Johnson Professorship at the University of Minnesota1996 IEEE Fellow for contributions to the fields of VLSI digital signal processing architectures, design methodologies and tools 1996-1998 IEEE Circuits and Systems Society Distinguished Lecturer 1992-1997 National Science Foundation Young Investigator Award1992-1994 McKnight - Land Grant Professorship at the Univ. of Minnesota
The inputs to the ALU are the data to be operated on (called operands) and a code from the control unit indicating which operation to perform. Its output is the result of the computation. In many designs the ALU also takes or generates as inputs or outputs a set of condition codes from or to a status register. These codes are used to indicate cases such as carry-in or carry-out, overflow, divide-by-zero, etc.
The system block diagram of a 4-bit ALU is shown in the Figure 1.6. ALU is a combinational circuit that performs logic and arithmetic micro-operations on a pair of n-bit operands (ex. A [3:0] and B [3:0]). The operations performed by an ALU are controlled by a set of function-select inputs. In this design a 4-bit ALU with 3 function-select inputs: Mode M, Select S1 and S0 inputs. The mode input M selects between a Logic (M=0) and Arithmetic (M=1) operation.
The synthesis & simulation is performed by using softwares like Xilinx 11.1 and ModelSim SE 5.7 which is further used for coding, testing and simulation of VHDL programs. The layout of 4- bit ALU has been shown in Figure 3.4 using Mentor Graphic 2007. The chip layout before fabrication is shown in Figure 3.4. The design was fabricated in AMI 1.5 mm CMOS process. The 4-Bit ALU occupies approximately an area of 830 x 935 mm2. SPICE simulations for the 4-bit ALU were done for post- layout extracted net lists. The RTL schematic block of 7-bit ALU is shown in Figure 3.1.
This paper presents design, optimization and implementation of 4-bit ALU. The increasing demand for low-power very large scale integration (VLSI) can be addressed at different design levels, such as the architectural, circuit, layout, and the process technology level. The simulation results shows improvement in delay of output signal & decrease the distortion of the waveforms at the output stages. Due to the major advantages the proposed design can be suitable in DSP applications.
For the Multiple-Input, Multiple Output systems, it is essential to design a new RF switch that is capable of operating with multiple antennas and frequencies as well as minimizing signal distortion and power consumption [6-8]. The excellent improvement in the frequency response of Si-CMOS devices has aggravated their use in the millimeter-wave regime such as high capacity wireless local area network, short range high data rate wireless personal area networks, and collision avoidance radar for automobiles. Using Si-CMOS for these applications allows for higher levels of integration and lower cost with improving the efficiency. Since for 65-nm technology has application of 60 GHz power amplifier designs [9,10], but recently few research group has demonstrated 60 GHz power amplifiers in 45-nm technologies.
In the design of DP4T DG RF CMOS switch structures with 45-nm technology for digital and analog, a transaction between speed and frequency response and circuit complexity is always encountered. The properties for RF CMOS switch design for the application in communication and designed results are presented and have been designed to optimize for the particular application [14]. A DP4T DG RF CMOS switch has the properties as fixed tuned matching networks, low quality factor matching networks, high power output, mounting flange packages, and silicon grease. Some bipolar RF CMOS transistors are suitable for automotive, commercial or general industrial applications.
In this paper, we present a comprehensive study of the RF switch performance of 45-nm low-power, high-speed double-pole four-throw double-gate radio-frequency complementary-metal-oxide-semiconductor (DP4T DG RF CMOS) switch. The DP4T DG RF CMOS switch structures with different aspect ratios for 45-nm technology and their layouts are studied to understand the effect of device geometry on working of switching properties. In this design transistor width increases for double-gate MOSFET such that peak power-added efficiency (PAE) and output power Pout decrease as these parameters decreases with increasing device width because of a reduction in fmax [15]. In a RF power amplifier, PAE is defined as the ratio of the difference of the output and input signal power to the DC power consumed. The RF power performance of 45-nm devices is shown to be very comparable to that of 65-nm devices.
The proposed switch contains CMOS in its architecture and needs only two control lines (V1, V2) of 1.2 V to control the signal traffic between two antennas and four ports as shown in Figure 1, hence, improving port isolation performance two times, compared to the DPDT switch and reducing signal distortion. In addition, signal fading effects can be reduced because sending identical signals through multiple antennas will most likely result in a high quality combined signal at the receiver end. For the design of DP4T DG RF CMOS switch, we design a
double-gate as shown in Figure 2. This shows the double-gate n-MOSFET. Similarly, we can design doublegate p-MOSFET. Now, we convert the Figure 1, DP4T switch using the basic double-gate transistor as shown in Figure 2, for DP4T DG RF CMOS switch as shown in Figure 3.
Since in the Figure 1, four transistors are used for two antennas. In this antenna using the CMOS functionalityat a time any one of transistor M1 or M3 will operate and in the same fashion any one of transistor M2 or M4 will operate. Same function is measured in the proposed DP4T DG RF CMOS switch as in Figure 3. This circuit is designed with a Micro-Cap evaluation 6.0 tool. We can find easily that CMOS based RF switches allow longer battery life than PIN diodes, because current consumption is significantly reduced and also about 60 percent smaller than the smallest GaAs RF switch on the market. Furthermore, our switch also experiences minimal distortion, negligible voltage fluctuation, and low power supply of only 1.2 V. In this switch with compare to Figure 1, for A_Tx and B_Tx, two p-MOS are designed for parallel combination and for A_Rx and B_Rx, two n-MOS are designed for parallel combination which is better selection. 153554b96e
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